Lin, Chenming: search on Z-Library

The world's largest scientific articles store. 70,000,000+ articles for free.

Don't use scam websites

1

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

Agarwal, Harshit, Kushwaha, Pragya, Duarte, Juan Pablo, Lin, Yen-Kai, Sachid, Angada B., Chang, Huan-Lin, Salahuddin, Sayeef, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Year:

2018

Language:

english

File:

PDF, 2.43 MB

english, 2018

2

[IEEE International Electron Devices Meeting. Technical Digest. IEDM - San Francisco, CA, USA (10-13 Dec. 2000)] International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) - Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectrics

Qiang Lu,, Lin, R., Ranade, P., Yee Chia Yeo,, Xiaofan Meng,, Takeuchi, H., Tsu-Jae King,, Chenming Hu,, Hongfa Luan,, Songjoo Lee,, Weiping Bai,, Choong-Ho Lee,, Dim-Lee Kwong,, Xin Guo,,

Year:

2000

Language:

english

File:

PDF, 337 KB

english, 2000

3

[IEEE 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) - Bangalore (2018.3.16-2018.3.17)] 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) - A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect

Kushwaha, Pragya, Agarwal, Harshit, Dabhi, Chetan Kumar, Lin, Yen-Kai, Duarte, J-P., Hu, Chenming, Chauhan, Yogesh Singh

Year:

2018

Language:

english

File:

PDF, 608 KB

english, 2018

4

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu

Journal:

Solid-State Electronics

Year:

2011

Language:

english

File:

PDF, 1.36 MB

english, 2011

5

Modeling Advanced FET Technology in a Compact Model

Dunga, M.V., Chung-Hsun Lin, Xuemei Xi, Lu, D.D., Niknejad, A.M., Chenming Hu

Journal:

IEEE Transactions on Electron Devices

Year:

2006

Language:

english

File:

PDF, 478 KB

english, 2006

6

[IEEE 2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, USA (11-13 June 2002)] 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) - 35 nm CMOS FinFETs

Fu-Liang Yang,, Haur-Ywh Chen,, Fang-Cheng Chen,, Yi-Lin Chan,, Kuo-Nan Yang,, Chih-Jian Chen,, Hun-Jan Tao,, Yang-Kyu Choi,, Mong-Song Liang,, Chenming Hu,

Year:

2002

Language:

english

File:

PDF, 301 KB

english, 2002

7

[IEEE 2007 IEEE Symposium on VLSI Technology - Kyoto, Japan (2007.06.12-2007.06.14)] 2007 IEEE Symposium on VLSI Technology - BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

Dunga, Mohan V., Lin, Chung-Hsun, Lu, Darsen D., Xiong, Weize, Cleavelin, C. R., Patruno, P., Hwang, Jiunn-Ren, Yang, Fu-Liang, Niknejad, Ali M., Hu, Chenming

Year:

2007

Language:

english

File:

PDF, 884 KB

english, 2007

8

[IEEE CICC Custom Integrated Circuits Conference - San Jose, CA, USA (21-24 Sept. 2003)] Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003. - A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Ke-Wei Su,, Yi-Ming Sheu,, Chung-Kai Lin,, Sheng-Jier Yang,, Wen-Jya Liang,, Xuemei Xi,, Chung-Shi Chiang,, Jaw-Kang Her,, Yu-Tai Chia,, Diaz, C.H., Chenming Hu,

Year:

2003

Language:

english

File:

PDF, 282 KB

english, 2003

9

[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Metal gate work function adjustment for future CMOS technology

Qiang Lu,, Lin, R., Ranade, P., Tsu-Jae King,, Chenming Hu,

Year:

2001

Language:

english

File:

PDF, 235 KB

english, 2001

10

[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Effects of high-κ dielectrics on the workfunctions of metal and silicon gates

Yee-Chia Yeo,, Ranade, P., Qiang Lu,, Lin, R., Tsu-Jae King,, Chenming Hu,

Year:

2001

Language:

english

File:

PDF, 223 KB

english, 2001

11

Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric

Qiang Lu,, Yee Chia Yeo,, Yang, K.J., Lin, R., Polishchuk, I., Tsu-Jae King,, Chenming Hu,, Song, S.C., Luan, H.F., Dim-Lee Kwong,, Xin Guo,, Zhijiong Luo,, Xiewen Wang,, Tso-Ping Ma,

Journal:

IEEE Electron Device Letters

Year:

2001

Language:

english

File:

PDF, 100 KB

english, 2001

12

[IEEE Proceedings of the IEEE 2004 Custom Integrated Circuits Conference - Orlando, FL, USA (3-6 Oct. 2004)] Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) - The next generation BSIM for sub-100nm mixed-signal circuit simulation

Xuemei Xi,, Jin He,, Dunga, M., Chung-Hsun Lin,, Heydari, B., Hui Wan,, Chan, M., Niknejad, A.M., Chenming Hu,

Year:

2004

Language:

english

File:

PDF, 318 KB

english, 2004

13

[IEEE 2011 IEEE International Electron Devices Meeting (IEDM) - Washington, DC, USA (2011.12.5-2011.12.7)] 2011 International Electron Devices Meeting - Bifacial CIGS (11% efficiency)/Si solar cells by Cd-free and sodium-free green process integrated with CIGS TFTs

Yu-Jen Hsiao,, Hsueh, Ting-Jen, Jia-Min Shieh,, Yu-Ming Yeh,, Chien-Chih Wang,, Bau-Tong Dai,, Wen-Wei Hsu,, Jing-Yi Lin,, Shen, Chang-Hong, Liu, C. W., Chenming Hu,, Fu-Liang Yang,

Year:

2011

Language:

english

File:

PDF, 2.42 MB

english, 2011

14

Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

Lin, Cheng-I, Khan, Asif Islam, Salahuddin, Sayeef, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Year:

2016

Language:

english

File:

PDF, 678 KB

english, 2016

15

[IEEE 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Hong Kong, Hong Kong (2016.8.3-2016.8.5)] 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Modeling of high voltage LDMOSFET using industry standard BSIM6 MOS model

Gupta, Chetan, Agarwal, Harshit, Chauhan, Yogesh S., Khandelwal, Sourabh, Lin, Yen-Kai, Hu, Chenming, Gillon, Renaud

Year:

2016

Language:

english

File:

PDF, 536 KB

english, 2016

16

[IEEE 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Hong Kong, Hong Kong (2016.8.3-2016.8.5)] 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model

Agarwal, Harshit, Kushwaha, Pragya, Chauhan, Yogesh S., Khandelwal, Sourabh, Duarte, Juan P., Lin, Yen-Kai, Chang, Huan-Lin, Hu, Chenming, Wu, Heng, Ye, Peide D.

Year:

2016

Language:

english

File:

PDF, 1.49 MB

english, 2016

17

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Gupta, Chetan, Agarwal, Harshit, Lin, Y. K., Ito, Akira, Hu, Chenming, Chauhan, Yogesh Singh

Journal:

Japanese Journal of Applied Physics

Year:

2017

Language:

english

File:

PDF, 3.13 MB

english, 2017

18

Comprehensive evaluation on effective leaching of critical metals from spent lithium-ion batteries

Gao, Wenfang, Liu, Chenming, Cao, Hongbin, Zheng, Xiaohong, Lin, Xiao, Wang, Haijuan, Zhang, Yi, Sun, Zhi

Journal:

Waste Management

Year:

2018

Language:

english

File:

PDF, 1.34 MB

english, 2018

19

Selective Recovery of Lithium from Spent Lithium Iron Phosphate Batteries: A Sustainable Process

Yang, Yongxia, Meng, Xiangqi, Cao, Hongbin, Lin, Xiao, Liu, Chenming, Sun, Yong, Zhang, Yi, Sun, Zhi

Journal:

Green Chemistry

Year:

2018

Language:

english

File:

PDF, 1.27 MB

english, 2018

20

[IEEE 2018 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2018.6.18-2018.6.22)] 2018 IEEE Symposium on VLSI Technology - Response Speed of Negative Capacitance FinFETs

Kwon, Daewoong, Liao, Yu-Hung, Lin, Yen-Kai, Duarte, Juan Pablo, Chatterjee, Korok, Tan, Ava J., Yadav, Ajay K., Hu, Chenming, Krivokapic, Zoran, Salahuddin, Sayeef

Year:

2018

Language:

english

File:

PDF, 695 KB

english, 2018

21

Whole-Process Pollution Control for Cost-Effective and Cleaner Chemical Production—A Case Study of the Tungsten Industry in China

Cao, Hongbin, Zhao, He, Zhang, Di, Liu, Chenming, Lin, Xiao, Li, Yuping, Ning, Pengge, Sun, Jiajun, Zhang, Yi, Sun, Zhi

Journal:

Engineering(BeiJing)

Year:

2019

Language:

english

File:

PDF, 1.19 MB

english, 2019

22

Patterned iridium oxide film as neural electrode interface: Biocompatibility and improved neurite outgrowth with electrical stimulation

Chen, Cen, Ruan, Shichao, Bai, Xue, Lin, Chenming, Xie, Chungang, Lee, In-Seop

Journal:

Materials Science and Engineering: C

Year:

2019

File:

PDF, 1.91 MB

2019

23

Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

Mansun Chan, Pin Su, Hui Wan, Chung-Hsun Lin, Samuel K.-H. Fung, Ali M. Niknejad, Chenming Hu, Ping K. Ko

Journal:

Solid-State Electronics

Year:

2004

Language:

english

File:

PDF, 669 KB

english, 2004

24

Monochromatic image of helium in argon–helium mixture arc plasma

Xu Chenming, Gao Hongming, Zhang Guangjun, Wu Lin

Journal:

Year:

2005

Language:

english

File:

PDF, 276 KB

english, 2005

25

Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects

Kai Chen, Chenming Hu, Peng Fang, Min Ren Lin, Wollesen, D.L.

Journal:

IEEE Transactions on Electron Devices

Year:

1997

Language:

english

File:

PDF, 94 KB

english, 1997

26

Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density

Min-Cheng Chen, Chia-Yi Lin, Bo-Yuan Chen, Chang-Hsien Lin, Guo-Wei Huang, Chia-Hua Ho, Tahui Wang, Chenming Hu, Fu-Liang Yang

Journal:

IEEE Electron Device Letters

Year:

2012

Language:

english

File:

PDF, 228 KB

english, 2012

27

Novel dual-metal gate technology using Mo-MoSix combination

Tzung-Lin Li, Wu-Lin Ho, Hung-Bin Chen, Wang, H.C.-H., Chun-Yen Chang, Chenming Hu

Journal:

IEEE Transactions on Electron Devices

Year:

2006

Language:

english

File:

PDF, 486 KB

english, 2006

28

Performance-Aware Corner Model for Design for Manufacturing

Chung-Hsun Lin, Dunga, M.V., Lu, D.D., Niknejad, A.M., Chenming Hu

Journal:

IEEE Transactions on Electron Devices

Year:

2009

Language:

english

File:

PDF, 834 KB

english, 2009

29

[IEEE 2011 IEEE International Electron Devices Meeting (IEDM) - Washington, DC, USA (2011.12.5-2011.12.7)] 2011 International Electron Devices Meeting - Nearly defect-free Ge gate-all-around FETs on Si substrates

Shu-Han Hsu,, Chun-Lin Chu,, Wen-Hsien Tu,, Fu, Yen-Chun, Po-Jung Sung,, Hung-Chih Chang,, Yen-Ting Chen,, Li-Yaw Cho,, Hsu, William, Luo, Guang-Li, Liu, C. W., Chenming Hu,, Fu-Liang Yang,

Year:

2011

Language:

english

File:

PDF, 2.55 MB

english, 2011

30

[IEEE SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest - Cambridge, MA, USA (8-10 Sept. 1997)] SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest - Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Kai Chen,, Chenming Hu,, Peng Fang,, Gupta, A., Ming Ren Lin,, Wollesen, D.L.

Year:

1997

Language:

english

File:

PDF, 289 KB

english, 1997

31

Compact Modeling of Variation in FinFET SRAM Cells

Lu, D.D., Chung-Hsun Lin, Niknejad, A.M., Chenming Hu

Journal:

IEEE Design & Test of Computers

Year:

2010

Language:

english

File:

PDF, 729 KB

english, 2010

32

[IEEE 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - San Diego, CA, USA (2009.09.9-2009.09.11)] 2009 International Conference on Simulation of Semiconductor Processes and Devices - Design of FinFET SRAM Cells Using a Statistical Compact Model

Lu, Darsen D., Lin, Chung-Hsun, Yao, Shijing, Xiong, Weize, Bauer, Florian, Cleavelin, Cloves R., Niknejad, Ali M., Hu, Chenming

Year:

2009

Language:

english

File:

PDF, 505 KB

english, 2009

33

[IEEE 2007 IEEE International Electron Devices Meeting - Washington, DC, USA (2007.12.10-2007.12.12)] 2007 IEEE International Electron Devices Meeting - A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation

Lu, Darsen D., Dunga, Mohan V., Lin, Chung-Hsun, Niknejad, Ali M., Hu, Chenming

Year:

2007

Language:

english

File:

PDF, 3.67 MB

english, 2007

34

[IEEE 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. - Beijing, China (Oct. 18-21, 2004)] Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. - BSIM5 MOSFET model

Xuemei Xi,, Jin He,, Dunga, M., Hui Wan,, Mansun Chan,, Chung-Hsun Lin,, Heydari, B., Niknejad, A.M., Chenming Hu,

Year:

2004

Language:

english

File:

PDF, 714 KB

english, 2004

35

[IEEE 2012 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2012.12.10-2012.12.13)] 2012 International Electron Devices Meeting - Interfacial layer-free ZrO2 on Ge with 0.39-nm EOT, κ∼43, ∼2×10−3 A/cm2 gate leakage, SS =85 mV/dec, Ion/Ioff =6×105, and high strain response

Lin, Cheng-Ming, Chang, Hung-Chih, Chen, Yen-Ting, Wong, I-Hsieh, Lan, Huang-Siang, Luo, Shih-Jan, Lin, Jing-Yi, Tseng, Yi-Jen, Liu, C. W., Hu, Chenming, Yang, Fu-Liang

Year:

2012

Language:

english

File:

PDF, 1.29 MB

english, 2012

36

Bistable Resistive Switching in Al[sub 2]O[sub 3] Memory Thin Films

Lin, Chih-Yang, Wu, Chen-Yu, Wu, Chung-Yi, Hu, Chenming, Tseng, Tseung-Yuen

Journal:

Journal of The Electrochemical Society

Year:

2007

Language:

english

File:

PDF, 159 KB

english, 2007

37

[IEEE IEEE International Electron Devices Meeting - San Francisco, CA, USA (8-11 Dec. 2002)] Digest. International Electron Devices Meeting, - FinFET scaling to 10 nm gate length

Bin Yu,, Leland Chang,, Ahmed, S., Haihong Wang,, Bell, S., Chih-Yuh Yang,, Tabery, C., Chau Ho,, Qi Xiang,, Tsu-Jae King,, Bokor, J., Chenming Hu,, Ming-Ren Lin,, Kyser, D.

Year:

2002

Language:

english

File:

PDF, 277 KB

english, 2002

38

[IEEE 1997 55th Annual Device Research Conference Digest - Fort Collins, CO, USA (23-25 June 1997)] 1997 55th Annual Device Research Conference Digest - Experimental and analytical studies on CMOS scaling in deep submicron regime including quantum and polysilicon gate depletion effects

Kai Chen,, Chenming Hu,, Peng Fang,, Gupta, A., Ming Pen Lin,, Wollesen, D.

Year:

1997

Language:

english

File:

PDF, 225 KB

english, 1997

39

Building 3D Layer-by-Layer Graphene–Gold Nanoparticle Hybrid Architecture with Tunable Interlayer Distance

Xue, Chenming, Gao, Min, Xue, Yuhua, Zhu, Lin, Dai, Liming, Urbas, Augustine, Li, Quan

Journal:

The Journal of Physical Chemistry C

Year:

2014

Language:

english

File:

PDF, 3.96 MB

english, 2014

40

[IEEE Comput. Soc 5th International Symposium on Quality Electronic Design - San Jose, CA, USA (22-24 March 2004)] SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720) - A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs using SPP approach

Jin He,, Xuemei, X., Mansun Chan,, Chung-Hsun Lin,, Ali Niknejad,, Chenming Hu,

Year:

2004

Language:

english

File:

PDF, 400 KB

english, 2004

41

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

Yu Cao,, Xuejue Huang,, Chang, N.H., Shen Lin,, Nakagawa, O.S., Weize Xie,, Sylvester, D., Chenming Hu,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 530 KB

english, 2002

42

[IEEE 2001 International Semiconductor Device Research Symposium. Symposium - Washington, DC, USA (5-7 Dec. 2001)] 2001 International Semiconductor Device Research Symposium. Symposium Proceedings (Cat. No.01EX497) - Deep-submicron CMOS process integration of HfO/sub 2/ gate dielectric with poly-Si gate

Qiang Lu,, Lin, R., Takeuchi, H., Tsu-Jae King,, Chenming Hu,, Onishi, K., Rino Choi,, Chang-Seok Kang,, Lee, J.C.

Year:

2001

Language:

english

File:

PDF, 393 KB

english, 2001

43

An adjustable work function technology using Mo gate for CMOS devices

Lin, R., Qiang Lu,, Ranade, P., Tsu-Jae King,, Chenming Hu,

Journal:

IEEE Electron Device Letters

Year:

2002

Language:

english

File:

PDF, 51 KB

english, 2002

44

[IEEE 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers - Hsinchu, Taiwan (18-20 April 2001)] 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) - Nanoscale CMOS at low temperature: design, reliability, and scaling trend

Bin Yu,, Haihong Wang,, Riccobene, C., Hyeon-Seag Kim,, Qi Xiang,, Ming-Ren Lin,, Leland Chang,, Chenming Hu,

Year:

2001

Language:

english

File:

PDF, 272 KB

english, 2001

45

[IEEE 2002 IEEE International Reliability Physics Symposium Proceedings. 40th Annual - Dallas, TX, USA (7-11 April 2002)] 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320) - Hot carrier reliability of n-MOSFET with ultra-thin HfO/sub 2/ gate dielectric and poly-Si gate

Qiang Lu,, Takeuchi, H., Lin, R., Tsu-Jae King,, Chenming Hu,, Onishi, K., Rino Choi,, Chang-Seok Kang,, Lee, J.C.

Year:

2002

Language:

english

File:

PDF, 153 KB

english, 2002

46

[IEEE 2008 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA) - Hsinchu, Taiwan (2008.04.21-2008.04.23)] 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) - Statistical Compact Modeling of Variations in Nano MOSFETs

Lin, Chung-Hsun, Dunga, Mohan V., Lu, Darsen, Niknejad, Ali M., Hu, Chenming

Year:

2008

Language:

english

File:

PDF, 1.50 MB

english, 2008

47

[IEEE 2012 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2012.12.10-2012.12.13)] 2012 International Electron Devices Meeting - Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels

Hsu, Shu-Han, Chang, Hung-Chih, Chu, Chun-Lin, Chen, Yen-Ting, Tu, Wen-Hsien, Hou, Fu Ju, Lo, Chih Hung, Sung, Po-Jung, Chen, Bo-Yuan, Huang, Guo-Wei, Luo, Guang-Li, Liu, C. W., Hu, Chenming, Yang, Fu

Year:

2012

Language:

english

File:

PDF, 1.45 MB

english, 2012

48

Electrical Characteristics of n, p-In0.53Ga0.47As MOSCAPs With In Situ PEALD-AlN Interfacial Passivation Layer

Luc, Quang Ho, Chang, Edward Yi, Trinh, Hai Dang, Lin, Yueh Chin, Nguyen, Hong Quan, Wong, Yuen Yee, Do, Huy Binh, Salahuddin, Sayeef, Hu, Chenming Calvin

Journal:

IEEE Transactions on Electron Devices

Year:

2014

Language:

english

File:

PDF, 2.13 MB

english, 2014

49

[IEEE International Electron Devices Meeting. Technical Digest - Washington, DC, USA (2-5 Dec. 2001)] International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) - High performance 0.1 μm PD SOI tunneling-biased MOSFETs (TBMOS)

Kuo-Nan Yang,, Yi-Lin Chan,, Yu-Lin Chu,, Hou-Yu Chen,, Fu-Liang Yang,, Chenming Hu,

Year:

2001

Language:

english

File:

PDF, 274 KB

english, 2001

50

[IEEE International Electron Devices Meeting. Technical Digest. IEDM - San Francisco, CA, USA (10-13 Dec. 2000)] International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) - RLC signal integrity analysis of high-speed global interconnects [CMOS]

Xuejue Huang,, Yu Cao,, Sylvester, D., Shen Lin,, King, T.-J., Chenming Hu,

Year:

2000

Language:

english

File:

PDF, 374 KB

english, 2000